SX1303CTSXXXGW1
The LoRa® Corecell gateway Fine Timestamp reference design is a complete indoor and outdoor gateway turnkey solution reference design provided for US, EU and China ISM bands. The reference design is based on SX1303.
No evaluation kit available for purchase
Available reference design file package
功能
- 精细时间戳
- 与传统产品相比,功耗降低了 10 倍
- 最大 TX 输出功率 (CN490) = +17dBm
- 最大 TX 输出功率 (EU868/US915) = +27dBm
- 接收 8 个 LoRa 通道的多数据速率(SF5 ~ SF12 / 125 同时 kHz)+ 2 个单数据速率(LoRa 250 / 500kHz 和 FSK 50kbps)
- 典型灵敏度等级 (CN490):
- SF12 BW 125kHz 时为 -141dBm
- SF7 BW 125kHz 时为 -12dBm
- FSK 50kbps 时为 -110dBm
- 典型灵敏度等级 (EU868/US915):
- SF12 BW 125kHz 时为 -140dBm
- SF7 BW 125kHz 时为 -125dBm
- FSK 50kbps 时为 -110dBm
- 智能家居
- 楼宇自动化
- 工厂自动化
应用
Datasheets & Documentation
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资源
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The LoRaWAN-based gateway is the physical layer (PHY) interface for the LoRaWAN network server (LNS). On the one hand, it listens to certain parts of the radio spectrum and decodes LoRa®-modulated signals originating from LoRa-based sensors. On the other hand, the gateway transmits messages from the network down to a sensor as LoRa-modulated signals.
LoRaWAN 区域参数中规定了接收和传输这些信号的确切参数。由于世界不同地区有不同的监管要求,因此参数因地区而异。
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