概览
The LoRa® Corecell gateway Fine Timestamp reference design is a complete indoor and outdoor gateway turnkey solution reference design provided for US, EU and China ISM bands. The reference design is based on SX1303.
No evaluation kit available for purchase
Available reference design file package
功能
- 精细时间戳
- 与传统产品相比，功耗降低了 10 倍
- 最大 TX 输出功率 (CN490) = +17dBm
- 最大 TX 输出功率 (EU868/US915) = +27dBm
- 接收 8 个 LoRa 通道的多数据速率（SF5 ~ SF12 / 125 同时 kHz）+ 2 个单数据速率（LoRa 250 / 500kHz 和 FSK 50kbps）
- 典型灵敏度等级 (CN490)：
- SF12 BW 125kHz 时为 -141dBm
- SF7 BW 125kHz 时为 -12dBm
- FSK 50kbps 时为 -110dBm
- 典型灵敏度等级 (EU868/US915)：
- SF12 BW 125kHz 时为 -140dBm
- SF7 BW 125kHz 时为 -125dBm
- FSK 50kbps 时为 -110dBm
| 文档 | Release Date | Type |  |
|---|---|---|---|
| 5 Things You Need to Know About LoRaWAN®-Based Gateways | 2024-06-06 | | |
| 中国 FineTimeStamp 网关（USB 版）用 Corecell 参考设计性能报告 | 2020-12-18 | | |
| 欧洲 FineTimeStamp 网关（USB 版）用 Corecell 参考设计性能报告 | 2020-12-18 | | |
| 美国 FineTimeStamp 网关（USB 版）用 Corecell 参考设计性能报告 | 2020-12-18 | | |
| 中国 FineTimeStamp 网关（USB 版）用 Corecell 参考设计产品文件夹 | 2020-12-18 | ZIP | |
| 欧洲 FineTimeStamp 网关（USB 版）用 Corecell 参考设计产品文件夹 | 2021-10-21 | ZIP | |
| 美国 FineTimeStamp 网关（USB 版）用 Corecell 参考设计产品文件夹 | 2021-10-21 | ZIP | |
Inventory
| Product | 国家/地区 | 经销商 | Qty | Buy |
|---|
资源
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